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High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers ADG5408/ADG5409
FEATURES
Latch-up proof 8 kV human body model (HBM) ESD rating Low on resistance (13.5 ) 9 V to 22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at 15 V, 20 V, +12 V, and +36 V VSS to VDD analog signal range
S1
FUNCTIONAL BLOCK DIAGRAMS
ADG5408
S1A DA S4A D S1B DB S8 1-OF-8 DECODER S4B 1-OF-4 DECODER
09206-001
ADG5409
APPLICATIONS
Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems
A0 A1 A2 EN
A0
A1
EN
Figure 1.
GENERAL DESCRIPTION
The ADG5408/ADG5409 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The ADG5408 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A0, A1, and A2. The ADG5409 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A0 and A1. An EN input on both devices enables or disables the device. When EN is disabled, all channels switch off. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the parts suitable for video signal switching. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. The ADG5408/ADG5409 do not have VL pins; rather, the logic power supply is generated internally by an on-chip voltage generator.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Low RON. Dual-supply operation. For applications where the analog signal is bipolar, the ADG5408/ADG5409 can be operated from dual supplies up to 22 V. Single-supply operation. For applications where the analog signal is unipolar, the ADG5408/ADG5409 can be operated from a single rail power supply up to 40 V. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required.
2. 3.
4.
5. 6.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADG5408/ADG5409 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Specifications..................................................................................... 3 15 V Dual Supply ....................................................................... 3 20 V Dual Supply ....................................................................... 4 12 V Single Supply ........................................................................ 5 36 V Single Supply ........................................................................ 6 Continuous Current per Channel, Sx or D ............................... 8 Absolute Maximum Ratings ............................................................9 ESD Caution...................................................................................9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 12 Test Circuits ..................................................................................... 16 Terminology .................................................................................... 18 Trench Isolation .............................................................................. 19 Applications Information .............................................................. 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21
REVISION HISTORY
9/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADG5408/ADG5409 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth ADG5408 ADG5409 Insertion Loss CS (Off ) CD (Off ) ADG5408 ADG5409 2.0 0.8 0.002 0.1 3 170 217 140 175 130 161 50 115 -60 -60 0.01 V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 25C -40C to +85C -40C to +125C VDD to VSS 13.5 15 0.3 0.8 1.8 2.2 0.05 0.25 0.1 0.4 0.1 0.4 18 22 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max Test Conditions/Comments
VS = 10 V, IS = -10 mA; see Figure 26 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA
1.3 2.6
1.4 3
VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = m 10 V; see Figure 29 VS = 10 V, VD = m 10 V; see Figure 29 VS = VD = 10 V; see Figure 25
1 4 4
7 30 30
VIN = VGND or VDD
258 213 183
292 242 198 16
RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS = 10 V; see Figure 34 RL = 300 , CL = 35 pF VS = 10 V; see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 k, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
50 87 0.9 15 102 50
Rev. 0 | Page 3 of 24
MHz typ MHz typ dB typ pF typ pF typ pF typ
RL = 50 , CL = 5 pF, f = 1 MHz; Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz
ADG5408/ADG5409
Parameter CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C 133 81 45 55 0.001
-40C to +85C
-40C to +125C
Unit pF typ pF typ A typ A max A typ A max V min/V max
Test Conditions/Comments VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
70 1 9/22
Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = -20 V 10%, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk 25C -40C to +85C -40C to +125C VDD to VSS 12.5 14 0.3 0.8 2.3 2.7 0.1 0.25 0.15 0.4 0.15 0.4 17 21 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ
Rev. 0 | Page 4 of 24
Test Conditions/Comments
VS = 15 V, IS = -10 mA; see Figure 26 VDD = +18 V, VSS = -18 V VS = 15 V, IS = -10 mA
1.3 3.1
1.4 3.5
VS = 15 V, IS = -10 mA VDD = +22 V, VSS = -22 V VS = 15 V, VD = m15 V; see Figure 29 VS = 15 V, VD = m15 V; see Figure 29 VS = VD = 15 V; see Figure 25
1 4 4
7 30 30 2.0 0.8
0.002 0.1 3 160 207 140 165 133 153 38 155 -60 -60
VIN = VGND or VDD
237 194 174
262 218 189 11
RL = 300 , CL = 35 pF VS = 10 V; see Figure 32 RL = 300 , CL = 35 pF VS = 10 V; see Figure 34 RL = 300 , CL = 35 pF VS = 10 V; see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 33 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27
ADG5408/ADG5409
Parameter Total Harmonic Distortion + Noise -3 dB Bandwidth ADG5408 ADG5409 Insertion Loss CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD ISS VDD/VSS
1
25C 0.012
-40C to +85C
-40C to +125C
Unit % typ
Test Conditions/Comments RL = 1 k, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
50 88 0.8 17 98 48 128 80 50 70 0.001
MHz typ MHz typ dB typ pF typ pF typ pF typ pF typ pF typ A typ A max A typ V min/V max
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = -22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V
110 9/22
Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD 26 30 0.3 1 5.5 6.5 0.02 0.25 0.05 0.4 0.05 0.4 1 7 36 42 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ Test Conditions/Comments
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 10 V, IS = -10 mA; see Figure 26 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA
1.5 8
1.6 12
VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29 VS = VD = 1 V/10 V; see Figure 25
Drain Off Leakage, ID (Off )
4 4
30 30 2.0 0.8
Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN
0.002 0.1 3
VIN = VGND or VDD
Rev. 0 | Page 5 of 24
ADG5408/ADG5409
Parameter DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth ADG5408 ADG5409 Insertion Loss CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD VDD
1
25C 230 321 215 276 134 161 118 45 -60 -60 0.1
-40C to +85C
-40C to +125C
Unit ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ
Test Conditions/Comments RL = 300 , CL = 35 pF VS = 8 V; see Figure 32 RL = 300 , CL = 35 pF VS = 8 V; see Figure 34 RL = 300 , CL = 35 pF VS = 8 V; see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 33 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 k, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
388 345 187
430 397 209 55
35 74 -1.8 22 119 59 146 86 40 50
MHz typ MHz typ dB typ pF typ pF typ pF typ pF typ pF typ A typ A max V min/V max
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
65 9/40
Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON 25C -40C to +85C -40C to +125C 0 V to VDD 14.5 16 0.3 0.8 3.5 4.3 0.1 0.25 1 7
Rev. 0 | Page 6 of 24
Unit V typ max typ max typ max nA typ nA max
Test Conditions/Comments
19
23
On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off )
VS = 0 V to 30 V, IS = -10 mA; see Figure 26 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = -10 mA
1.3 5.5
1.4 6.5
VS = 0 V to 30 V, IS = -10 mA VDD =39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 29
ADG5408/ADG5409
Parameter Drain Off Leakage, ID (Off ) 25C 0.15 0.4 0.15 0.4 -40C to +85C -40C to +125C Unit nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ Test Conditions/Comments VS = 1 V/30 V, VD = 30 V/1 V; see Figure 29 VS = VD = 1 V/30 V; see Figure 25
4 4
30 30 2.0 0.8
Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tD Charge Injection, QINJ Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth ADG5408 ADG5409 Insertion Loss CS (Off ) CD (Off ) ADG5408 ADG5409 CD (On), CS (On) ADG5408 ADG5409 POWER REQUIREMENTS IDD VDD
1
0.002 0.1 3 187 242 160 195 147 184 53 150 -60 -60 0.4
VIN = VGND or VDD
257 219 184
281 237 190 17
RL = 300 , CL = 35 pF VS = 18 V; see Figure 32 RL = 300 , CL = 35 pF VS = 18 V; see Figure 34 RL = 300 , CL = 35 pF VS = 18 V; see Figure 34 RL = 300 , CL = 35 pF VS1 = VS2 = 18 V; see Figure 33 VS = 18 V, RS = 0 , CL = 1 nF; see Figure 35 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 27 RL = 1 k, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
45 76 -1 18 120 60 137 80 80 100
MHz typ MHz typ dB typ pF typ pF typ pF typ pF typ pF typ A typ A max V min/V max
RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V
130 9/40
Guaranteed by design; not subject to production test.
Rev. 0 | Page 7 of 24
ADG5408/ADG5409
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 5. ADG5408
Parameter CONTINUOUS CURRENT, Sx OR D VDD = +15 V, VSS = -15 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = +20 V, VSS = -20 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 36 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
100 170 106 178 81 140 104 175
44 54 45 55 39 51 44 55
16 16 16 16 15 16 16 16
mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum
Table 6. ADG5409
Parameter CONTINUOUS CURRENT, Sx OR D VDD = +15 V, VSS = -15 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = +20 V, VSS = -20 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 12 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) VDD = 36 V, VSS = 0 V TSSOP (JA = 112.6C/W) LFCSP (JA = 30.4C/W) 25C 85C 125C Unit
75 130 79 136 60 105 78 133
37 49 38 50 32 44 38 50
15 16 15 16 14 16 15 16
mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum mA maximum
Rev. 0 | Page 8 of 24
ADG5408/ADG5409 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 7.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or D Pins ADG5408 ADG5409 Continuous Current, Sx or D2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, JA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free
1
Rating 48 V -0.3 V to +48 V +0.3 V to -48 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 370 mA (pulsed at 1 ms, 10% duty cycle maximum) 275 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% -40C to +125C -65C to +150C 150C 112.6C/W 30.4C/W 260(+0/-5)C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Overvoltages at the Ax, EN, Sx, and D pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5.
Rev. 0 | Page 9 of 24
ADG5408/ADG5409 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
16 EN 15 A0 14 A1
A0 1 EN 2 VSS
3 16 15 14
A1 A2 GND VDD S5 S6 S7
09206-002
S1 4 S2 5 S3 6 S4 7 D8
ADG5408
TOP VIEW (Not to Scale)
13 12 11 10 9
VSS 1 S1 2 S2 3 S3 4
PIN 1 INDICATOR
13 A2
12 GND 11 VDD 10 S5 9 S6
ADG5408
TOP VIEW (Not to Scale)
S8
Figure 2. ADG5408 Pin Configuration (TSSOP)
Figure 3. ADG5408 Pin Configuration (LFCSP)
Table 8. ADG5408 Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Mnemonic A0 EN VSS S1 S2 S3 S4 D S8 S7 S6 S5 VDD GND A2 A1 Exposed Pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1. This pin can be an input or an output. Source Terminal 2. This pin can be an input or an output. Source Terminal 3. This pin can be an input or an output. Source Terminal 4. This pin can be an input or an output. Drain Terminal. This pin can be an input or an output. Source Terminal 8. This pin can be an input or an output. Source Terminal 7. This pin can be an input or an output. Source Terminal 6. This pin can be an input or an output. Source Terminal 5. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5408 Truth Table
A2 X 0 0 0 0 1 1 1 1 A1 X 0 0 1 1 0 0 1 1 A0 X 0 1 0 1 0 1 0 1 EN 0 1 1 1 1 1 1 1 1 On Switch None 1 2 3 4 5 6 7 8
Rev. 0 | Page 10 of 24
09206-003
NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
S7 8
S8 7
S4 5
D6
ADG5408/ADG5409
16 EN 15 A0
A0 1 EN 2 VSS S1A S2A S3A S4A
3 4 5 6 7 16 15 14
A1 GND VDD S1B S2B S3B S4B
09206-004
ADG5409
TOP VIEW (Not to Scale)
13 12 11 10 9
VSS 1 S1A 2 S2A 3 S3A 4
PIN 1 INDICATOR
13 GND
14 A1
12 VDD 11 S1B 10 S2B 9 S3B
ADG5409
TOP VIEW (Not to Scale)
S4A 5
Figure 4. ADG5409 Pin Configuration (TSSOP)
Figure 5. ADG5409 Pin Configuration (LFCSP)
Table 10. ADG5409 Pin Function Descriptions
Pin No. TSSOP LFCSP 1 15 2 16 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 EP Mnemonic A0 EN VSS S1A S2A S3A S4A DA DB S4B S3B S2B S1B VDD GND A1 Exposed Pad Description Logic Control Input. Active High Digital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. Source Terminal 1A. This pin can be an input or an output. Source Terminal 2A. This pin can be an input or an output. Source Terminal 3A. This pin can be an input or an output. Source Terminal 4A. This pin can be an input or an output. Drain Terminal A. This pin can be an input or an output. Drain Terminal B. This pin can be an input or an output. Source Terminal 4B. This pin can be an input or an output. Source Terminal 3B. This pin can be an input or an output. Source Terminal 2B. This pin can be an input or an output. Source Terminal 1B. This pin can be an input or an output. Most Positive Power Supply Potential. Ground (0 V) Reference. Logic Control Input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5409 Truth Table
A1 X 0 0 1 1 A0 X 0 1 0 1 EN 0 1 1 1 1 On Switch Pair None 1 2 3 4
Rev. 0 | Page 11 of 24
09206-005
NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
S4B 8
DA 6
DB 7
DA 8
DB
ADG5408/ADG5409 TYPICAL PERFORMANCE CHARACTERISTICS
25 TA = 25C VDD = +9V VSS = -9V 20
ON RESISTANCE () ON RESISTANCE ()
16
TA = 25C
VDD = +10V VSS = -10V
14 12 10 8 6 4 2
VDD = 32.4V VSS = 0V VDD = 36V VSS = 0V VDD = 39.6V VSS = 0V
VDD = +11V VSS = -11V 15
10
VDD = +13.5V VSS = -13.5V VDD = +16.5V VSS = -16.5V
VDD = +15V VSS = -15V
5
09206-028
-14
-10
-6
-2
2
6
10
14
18
0
5
10
15
20
25
30
35
40
45
VS, VD (V)
VS, VD (V)
Figure 6. RON as a Function of VS, VD (Dual Supply)
16
TA = 25C
Figure 9. RON as a Function of VS, VD (Single Supply)
25
14 12
VDD = +18V VSS = -18V
20
ON RESISTANCE ()
10 8 6 4
VDD = +20V VSS = -20V VDD = +22V VSS = -22V
ON RESISTANCE ()
TA = +125C 15 TA = +85C TA = +25C 10 TA = -40C 5
2 0 -25
09206-029
-20
-15
-10
-5
0 VS, VD (V)
5
10
15
20
25
-5
0 VS, VD (V)
5
10
15
Figure 7. RON as a Function of VS, VD (Dual Supply)
-35
Figure 10. RON as a Function of VS (VD) for Different Temperatures, 15 V Dual Supply
25 VDD = +20V VSS = -20V
TA = 25C VDD = 9V VSS = 0V
-30 -25
VDD = 10V VSS = 0V
VDD = 10.8V VSS = 0V
20
ON RESISTANCE ()
ON RESISTANCE ()
-20 -15
VDD = 13.2V VSS = 0V VDD = 12V VSS = 0V VDD = 11V VSS = 0V
15
TA = +125C TA = +85C
10
TA = +25C TA = -40C
-10 -5
5
09206-023
0
-2
-4
-6
-8 VS, VD (V)
-10
-12
-14
-15
-10
-5
0 VS, VD (V)
5
10
15
20
Figure 8. RON as a Function of VS, VD (Single Supply)
Figure 11. RON as a Function of VS (VD) for Different Temperatures, 20 V Dual Supply
Rev. 0 | Page 12 of 24
09206-024
0
0 -20
09206-030
VDD = +15V VSS = -15V 0 -15 -10
09206-027
0 -18
0
ADG5408/ADG5409
40 35
1
VDD = +20V VSS = -20V VBIAS = +15V/-15V
ID, IS (ON) + + IS (OFF) + -
25 20 15 10 5 0
TA = +85C TA = +25C TA = -40C
LEAKAGE CURRENT (nA)
30
TA = +125C
0
ID (OFF) - + IS (OFF) - +
ON RESISTANCE ()
-1
ID, IS (ON) - -
-2
ID (OFF) + -
VDD = 12V VSS = 0V 0 2 4 6 VS, VD (V) 8 10 12
09206-031
0
25
50
75
100
125
TEMPERATURE (C)
Figure 12. RON as a Function of VS (VD) for Different Temperatures, 12 V Single Supply
25
Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply
0.5
VDD = 36V VSS = 0V
VDD = 12V VSS = 0V VBIAS = 1V/10V
ID, IS (ON) + + IS (OFF) + -
20
0
LEAKAGE CURRENT (nA)
ON RESISTANCE ()
15
TA = +125C TA = +85C
ID (OFF) - + -0.5 IS (OFF) - + ID, IS (ON) - - -1.0 ID (OFF) + -
10
TA = +25C TA = -40C
5
-1.5
09206-032
0
5
10
15
20 VS, VD (V)
25
30
35
40
0
25
50
75
100
125
TEMPERATURE (C)
Figure 13. RON as a Function of VD (VS) for Different Temperatures, 36 V Single Supply
0.5
VDD = +15V VSS = -15V VBIAS = +10V/-10V ID, IS (ON) + + IS (OFF) + -
LEAKAGE CURRENT (nA)
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
1
VDD = +36V VSS = 0V VBIAS = 1V/30V
ID, IS (ON) + +
IS (OFF) + -
0
LEAKAGE CURRENT (nA)
0 ID (OFF) - +
-0.5
IS (OFF) - +
ID (OFF) - +
IS (OFF) - + -1
ID, IS (ON) - -
-1.0
ID (OFF) + -
ID, IS (ON) - -
-2
ID (OFF) + -
-1.5
09206-034
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
Rev. 0 | Page 13 of 24
09206-036
-2.0
-3
09206-033
0
-2.0
09206-035
-3
ADG5408/ADG5409
TA = 25C V = +15V -10 VDD = -15V SS
0
0 -10 -20 -30
TA = 25C VDD = +15V VSS = -15V
-20
OFF ISOLATION (dB)
-30 -40 -50 -60 -70 -80 -90
09206-021
ACPSRR (dB)
-40 -50 -60 -70 -80 -90
NO DECOUPLING CAPACITORS DECOUPLING CAPACITORS
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k FREQUENCY (Hz)
1M
10M
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
0 -10 -20
CROSSTALK (dB) 0.12
Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply
TA = 25C VDD = +15V VSS = -15V
0.10 LOAD = 1k TA = 25C 0.08 THD + N (%)
VDD = 12V, VSS = 0V, VS = 6V p-p
-30 -40 -50 -60 -70 -80 -90
0.06 VDD = 36V, VSS = 0V, VS = 18V p-p 0.04
0.02
VDD = 15V, VSS = 15V, VS = 15V p-p VDD = 20V, VSS = 20V, VS = 20V p-p
09206-026
100k
1M
10M
100M
1G
0
5
10 FREQUENCY (kHz)
15
20
FREQUENCY (Hz)
Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply
300
TA = 25C VDD = +20V VSS = -20V 0
Figure 22. THD + N vs. Frequency
TA = 25C V = +15V -0.5 VDD = -15V SS -1.0 ADG5409 ADG5408 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5
09206-019
250
CHARGE INJECTION (pC)
INSERTION LOSS (dB)
200
VDD = +36V VSS = 0V
-1.5
150
100
VDD = +12V VSS = 0V VDD = +15V VSS = -15V
50
10
0
10 VS (V)
20
30
40
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 20. Charge Injection vs. Source Voltage
Figure 23. Bandwidth
Rev. 0 | Page 14 of 24
09206-020
0 20
-5.0 1k
09206-025
-100 10k
0
09206-022
-100
-100
ADG5408/ADG5409
400 350 300 250
VDD = +12V, VSS = 0V VDD = +36V, VSS = 0V
TIME (ns)
200 150 100 50 0 -40
VDD = +15V, VSS = -15V VDD = +20V, VSS = -20V
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 24. tTRANSITION Times vs. Temperature
Rev. 0 | Page 15 of 24
09206-018
ADG5408/ADG5409 TEST CIRCUITS
ID (ON) NC Sx Dx A
09206-008
IS (OFF) A
VS
ID (OFF) Sx D A
VD
09206-007
NC = NO CONNECT
VD
Figure 25. On Leakage
VDD 0.1F VSS
Figure 29. Off Leakage
0.1F AUDIO PRECISION VDD VSS RS Sx
IDS IN V1 VIN Sx D
09206-006
D RL 10k GND VOUT
VS V p-p
VS
RON = V1/IDS
Figure 26. On Resistance
VDD
0.1F
Figure 30. THD + Noise Figure
VSS
0.1F
VDD 0.1F
VSS 0.1F NETWORK ANALYZER
NETWORK ANALYZER VOUT RL 50
VDD S1
VSS
VDD
D
VSS Sx
50 VS D VOUT
S2
RL 50
RL 50
VS
GND
GND
09206-014
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 27. Channel-to-Channel Crosstalk
VDD
0.1F VSS
Figure 31. Bandwidth
0.1F
NETWORK ANALYZER 50 Sx
D
VDD
VSS
50 VS VOUT
GND
RL 50
OFF ISOLATION = 20 log
VOUT VS
Figure 28. Off Isolation
09206-013
Rev. 0 | Page 16 of 24
09206-017
09206-015
ADG5408/ADG5409
VDD 3V ADDRESS DRIVE (VIN) 0V 50% 50% VIN 50 VSS
tr < 20ns tf < 20ns
A0 A1
VDD
VSS S1 S2 TO S7 VS1
A2
tTRANSITION
tTRANSITION
90%
S8
VS8 OUTPUT
ADG5408*
2.4V EN GND D
OUTPUT
300
35pF
09206-009
90%
*SIMILAR CONNECTION FOR ADG5409.
Figure 32. Address to Output Switching Times, tTRANSITION
VDD 3V ADDRESS DRIVE (VIN) 0V VIN 50 A0 S1 A1 S2 TO S7 A2 S8 80% OUTPUT 80% 2.4V EN GND VS VSS
VDD
VSS
ADG5408*
D
OUTPUT
300
35pF
09206-010
tD
*SIMILAR CONNECTION FOR ADG5409.
Figure 33. Break-Before-Make Delay, tD
VDD 3V ENABLE DRIVE (VIN) 0V 50% 50% A0 S1 A1 S2 TO S8 A2 VS VSS
VDD
VSS
tON (EN)
0.9VO OUTPUT
tOFF (EN)
0.9VO VIN 50 EN
ADG5408*
OUTPUT D GND 300 35pF
*SIMILAR CONNECTION FOR ADG5409.
Figure 34. Enable Delay, tON (EN), tOFF (EN)
VDD VSS
VDD 3V A0 A1 VIN A2
VSS
ADG5408*
VOUT QINJ = CL x VOUT VOUT VS VIN
09206-012
RS
Sx EN GND
D CL 1nF
VOUT
*SIMILAR CONNECTION FOR ADG5409.
Figure 35. Charge Injection
Rev. 0 | Page 17 of 24
09206-011
ADG5408/ADG5409 TERMINOLOGY
IDD IDD represents the positive supply current. ISS ISS represents the negative supply current. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON is the ohmic resistance between Terminal D and Terminal S. RON RON represents the difference between the RON of any two channels. RFLAT (ON) The difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN represents digital input capacitance. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) tOFF (EN) represents the delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by THD + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 18 of 24
ADG5408/ADG5409 TRENCH ISOLATION
In the ADG5408/ADG5409, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch.
NMOS PMOS
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER HANDLE WAFER
09206-016
Figure 36. Trench Isolation
Rev. 0 | Page 19 of 24
ADG5408/ADG5409 APPLICATIONS INFORMATION
The ADG54xx family switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5408/ADG5409 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from 9 V to 22 V. The ADG5408/ADG5409 (as well as select devices within the same family) achieve an 8 kV human body model ESD rating that provides a robust solution eliminating the need for separate protect circuitry designs in some applications.
Rev. 0 | Page 20 of 24
ADG5408/ADG5409 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.10 4.00 SQ 3.90 0.65 BSC 0.35 0.30 0.25
13 12 EXPOSED PAD 1 16
PIN 1 INDICATOR
PIN 1 INDICATOR
4 9 8 5
2.70 2.60 SQ 2.50
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.45 0.40 0.35
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADG5408BRUZ ADG5408BRUZ-REEL7 ADG5408BCPZ-REEL7 ADG5409BRUZ ADG5409BRUZ-REEL7 ADG5409BCPZ-REEL7
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
012909-B
Package Option RU-16 RU-16 CP-16-17 RU-16 RU-16 CP-16-17
Z = RoHS Compliant Part.
Rev. 0 | Page 21 of 24
ADG5408/ADG5409 NOTES
Rev. 0 | Page 22 of 24
ADG5408/ADG5409 NOTES
Rev. 0 | Page 23 of 24
ADG5408/ADG5409 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09206-0-9/10(0)
Rev. 0 | Page 24 of 24

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